Modern computer systems employ processors which are capable of operating at much higher rates of execution than large capacity main memories can support, and a low capacity, high-speed cache memory is commonly used in addition to a large capacity main memory to improve program execution speed. The cache memory stores a limited number of instruction or data words; and for each memory read operation, the cache memory is checked to determine if the information is available in the cache memory. If the information is there, it will be read from the cache memory; otherwise, it will be read from the main memory. If the information must be read from the main memory, the new information must replace existing information in the cache memory at some cache storage location. A satisfactory cache storage location for storing new information is identified by one of the several commonly used replacement algorithms, e.g., random replacement, least recently used, etc. In general, the least recently used replacement algorithm is considered to be the most efficient algorithm; however, implementation of this algorithm in a cost-effective manner without incurring large time delays in maintaining a priority of cache memory locations, with respect to which is the least recently used memory location, has proven difficult to achieve. In particular, it has proven difficult to design a cache memory which was capable of expansion in the field.